Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

Torsten Lehmann; Erik Bruun; Casper Dietrich

doi:10.1007/BF00158852

Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

Authors:

Lehmann, Torsten ;
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Department of Information Technology, Technical University of Denmark
Bruun, Erik ;
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0000-0001-5085-7094
Department of Information Technology, Technical University of Denmark
Dietrich, Casper
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GIGA A/S

DOI:

10.1007/BF00158852

Abstract:

In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier/sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning in this system is possible using very little additional hardware compared to the recall mode system.

Type:

Journal article

Language:

English

Published in:

Analog Integrated Circuits and Signal Processing, 1996, Vol 9, Issue 1, p. 55-63

Main Research Area:

Science/technology

Publication Status:

Published

Review type:

Peer Review

Submission year:

1996

Scientific Level:

Scientific

ID:

9701533

Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

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