{"controller"=>"catalog", "action"=>"show", "id"=>"8353056"}
  • EN
  • DA

Danish NationalResearch Database

  • Search Publications & Researchers
  • Open Access Indicator
  • Publications
  • Researchers
Example Finds records
water{} containing the word "water".
water supplies"{}" containing the phrase "water supplies".
author:"Doe, John"author:"{}" containing the prase "Doe, John" in the author field.
title:IEEEtitle:{} containing the word "IEEE" in the title field.
Need more help? Advanced search tutorial
  • Selected (0)
  • History

Hardware Compilation of Application-Specific Memory-Access Interconnect

    • Save to Mendeley
    • Export to BibTeX
    • Export to RIS
    • Email citation
Authors:
  • Venkataramani, Girish ;
    Close
    unknown
  • Bjerregaard, Tobias ;
    Close
    Department of Informatics and Mathematical Modeling, Technical University of Denmark
  • Chelcea, Tiberiu ;
    Close
    unknown
  • Goldstein, Seth C.
    Close
    unknown
DOI:
10.1109/TCAD.2006.870411
Abstract:
A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.
Type:
Journal article
Language:
English
Published in:
I E E E Transactions on Computer - Aided Design of Integrated Circuits and Systems, 2006, Vol 25, Issue 5, p. 756-771
Keywords:
Main Research Area:
Science/technology
Publication Status:
Published
Review type:
Peer Review
Submission year:
2006
Scientific Level:
Scientific
ID:
8353056

Full text access

  • Openaccess Elsewhere online
  • Doi Get publisher edition via DOI resolver
Checking for on-site access...

On-site access

At institution

  • Technical university of dk
Feedback

Sitemap

  • Search
    • Statistics
    • Tutorial
    • Data
    • FAQ
    • Contact
  • Open Access
    • Overview
    • Development
    • FAQ
    • Contact
  • About
    • Institutions
    • Release History
    • Cookies and privacy policy

Copyright © 1998–2018.

Fivu en