In this paper, a seven-level single-carrier and multi-modulation-wave sinusoidal pulsewidth modulation (SCMM-SPWM) strategy is proposed. In the negative half cycle of the modulation waves (MWs), dc offsets related to the amplitude of the carrier are set on the three MWs, respectively, to apply the same comparison logics of the MWs and carrier during positive and negative half cycles of the MWs. Thus, it is implemented with only one digital signal processor chip without any other attached logical circuit or controller. The reason for generating the zero-crossing voltage pulse disturbance (ZCVPD) in this strategy is analyzed, and the elimination of the ZCVPD is proposed and verified by experimental results. The spectral characters of the conventional multi-MW-based SPWM and the proposed one are originally derived and compared with each other by simulation in detail. The theoretical analysis, simulation, and experimental results indicate that the output characters of the proposed strategy are identical to those of the conventional one; it means that the proposed strategy can replace the conventional one while with the benefit of significantly reducing the cost and bulk of the implemental platform.
I E E E Transactions on Industrial Electronics, 2015, Vol 62, Issue 2, p. 982-990
PWM invertors; Cost reduction; Digital signal processing chips; Power system faults; Power system reliability