1 Department of Energy Technology, The Faculty of Engineering and Science, Aalborg University, VBN2 Power Electronic Systems, The Faculty of Engineering and Science, Aalborg University, VBN3 The Faculty of Engineering and Science (ENG), Aalborg University, VBN4 Islamic Azad University5 Gamesa, Ltd6 Ferdowsi University of Mashhad7 Islamic Azad University8 Ferdowsi University of Mashhad
The phase locked-loops (PLLs) are probably the most widely used synchronization technique in grid-connected applications. The main challenge associated with the PLLs is how to precisely and fast estimate the phase and frequency when the grid voltage is unbalanced and/or distorted. To overcome this challenge, incorporating moving average filter(s) (MAF) into the PLL structure has been proposed in some recent literature. A MAF is a linear-phase finite impulse response filter which can act as an ideal low-pass filter, if certain conditions hold. The main aim of this paper is to present the control design guidelines for a typical MAF-based PLL. The paper starts with the general description of MAFs. The main challenge associated with using the MAFs is then explained, and its possible solutions are discussed. The paper then proceeds with a brief overview of the different MAF-based PLLs. In each case, the PLL block diagram description is shown, the advantages and limitations are briefly discussed, and the tuning approach (if available) is evaluated. The paper then presents two systematic methods to design the control parameters of a typical MAF-based PLL: one for the case of using a proportional-integral (PI) type loopfilter (LF) in the PLL, and the other for the case of using a proportional-integral-derivative (PID) type LF. Finally, the paper compares the performance of a well-tuned MAF-based PLL when using the PI-type LF with the results of using the PID-type LF, which provides useful insights into their capabilities and limitations.
I E E E Transactions on Power Electronics, 2014, Vol 29, Issue 6, p. 2750-2763
Moving average filter (MAF); Phase-locked loop (PLL); Grid synchronization