More than twenty years of thorough research on the serialization of power semiconductor switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), have resulted into several different stacking concepts; all aiming towards the establishment of a high-efficient, high-voltage, fast-switching device. Among the prevailing stacking approaches lies the gate balancing core technique, which, in its initial form, demonstrated very good performance in strings of high-power IGBT modules, by magnetically coupling their gate electrodes. Recently, a revised version of the technique, introducing an additional design specification for the employed transformer, extended its effective applicability in low and medium power MOSFETs as well. In this paper the scalability of the revised gate balancing core technique is investigated via experiments conducted on a string of three off-the-self, non-matched MOSFETs, installed in an inductively loaded step-down converter. Furthermore, during the string composition and experimental testing, all design milestones related with the scaling-up process of the revised gate balancing core concept are distinctively highlighted and discussed.
Proceedings of the Ieee Energy Conversion Congress and Exposition, Ecce 2013, 2013, p. 3664-3770
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IEEE Energy Conversion Congress and Exposition (ECCE2013), 2013