Moradi, Farshad7; Vu Cao, Tuan3; Vatajelu, Elena Ioana4; Peiravi, Ali5; Mahmoodi, Hamid6; Wisland, Dag3
1 Department of Engineering, Science and Technology, Aarhus University2 Department of Engineering - Integrated Electronics, Department of Engineering, Science and Technology, Aarhus University3 University of Oslo4 Electronic Engineering Department, Universitat Politècnica de Catalunya, Spain5 Ferdowsi University of Mashhad6 San Frncisco State University7 Department of Engineering - Integrated Electronics, Department of Engineering, Science and Technology, Aarhus University
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose several domino logic circuit techniques to improve the robustness and performance along with leakage power. Lower total power consumption is achieved by utilizing proposed techniques. According to the simulations in TSMC 65 nm CMOS process, the proposed circuits increase noise immunity for wide OR gates by at least 3.5X and shows performance improvement of up to 20% compared to conventional domino logic circuits. For FinFET simulation TCAD tools have been used.