Petricca, Massimo4; Albicocco, Pietro4; Cardarilli, Gian Carlo4; Nannarelli, Alberto5; Re, Marco4
1 Department of Informatics and Mathematical Modeling, Technical University of Denmark2 Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3 Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark4 University of Roma ‘Tor Vergata’5 Department of Applied Mathematics and Computer Science, Technical University of Denmark
It is well known that the Residue Number System (RNS) provides an efficient implementation of parallel FIR filters especially when the filter order and the dynamic range are high. The two main drawbacks of RNS, need of converters and coding overhead, make a serialized implementation of the FIR filter potentially disadvantageous with respect to filters implemented in the conventional number systems. In this work, we show a number of solutions which demonstrate that the power efficiency of RNS FIR filters implemented serially is maintained in ASIC technology, while in modern FPGA technology RNS implementations are less efficient.
Conference Record - Asilomar Conference on Signals, Systems, and Computers, 2012, p. 1015-1019
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Asilomar Conference on Signals, Systems and Computers. Conference Record
46th Asilomar Conference on Signals, Systems and Computers, 2012