Albicocco, Pietro3; Cardarilli, Gian Carlo3; Nannarelli, Alberto4; Petricca, Massimo3; Re, Marco3
1 Department of Informatics and Mathematical Modeling, Technical University of Denmark2 Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3 University of Roma ‘Tor Vergata’4 Department of Applied Mathematics and Computer Science, Technical University of Denmark
In this paper a review of different techniques used to implement highly optimized DSP systems is presented. The case of study is the implementation of parallel FIR filters aimed to applications characterized by high speed and high selectivity in frequency where at the same time low power dissipation is mandatory. After a review of the possible "standard" optimization techniques, the paper addresses aggressive methodologies where power and area savings are obtained by introducing the concept of "Degrading Precision Arithmetic" (DPA). Three different approaches are discussed: DPA-I, based on selective bit freezing, DPA-II, based on VDD voltage scaling, and DPA-III, based on power gating. Some theoreticaVsimuiative analysis of the introduced arithmetic errors and some implementation results are shown. A discussion on the suitability of these methodologies on standard cell technologies and FPGAs is also addressed. In our experience, these techniques are well known in the scientific community, but they are not extensively known in the design communiy, and, consequently, they are scarcely utilized.
Conference Proceedings, 2011
Main Research Area:
Midwest Symposium on Circuits and Systems. Conference Proceedings
IEEE International Midwest Symposium on Circuits and Systems, 2011