1 Department of Informatics and Mathematical Modeling, Technical University of Denmark2 Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark3 Embedded Systems Engineering, Department of Applied Mathematics and Computer Science, Technical University of Denmark4 Department of Applied Mathematics and Computer Science, Technical University of Denmark
With the rising number of cores on a single chip the question on how to organize the communication among those cores becomes more and more relevant. A common solution is to use a network-on-chip (NoC) that provides communication bandwidth, routing, and arbitration among the cores. The use of NoCs in real-time systems is problematic, since the shared network and all cores connected to it have to be analyzed to derive time bounds of real-time tasks. We propose to use a statically scheduled, time-division-multiplexed NoC design that allows a decoupled analysis of individual real-time tasks. Our network provides virtual circuits between all cores. These virtual circuits are implemented by delivering messages periodically on a static, fixed routing schedule. Since the routing does not change, it can be pre-computed offline. This work focuses on the computation of routing schedules for symmetric NoC topologies, e.g., torus and hyper-cube. Due to the symmetry, the all-to-all communication can be modeled via simplified communication patterns that are concurrently processed by all routers. The scheduling problem is solved by a heuristic that tries to maximize the overlap of active patterns. Our experiments show that, for larger networks, our heuristic yields schedule lengths that are only 15% to 20% longer than theoretical lower bounds.
Proceedings of the 20th International Conference on Real-time and Network Systems (rtns 2012), 2012, p. 61-70
Main Research Area:
20th International Conference on Real-Time and Network Systems (RTNS 2012)