An improved design of virtual output impedance loop for droop-controlled parallel three-phase Voltage Source Inverters
- Authors:
- DOI:
- 10.1109/ECCE.2012.6342404
- Abstract:
- The virtual output impedance loop is known as an effective way to enhance the load sharing stability and quality of droop-controlled parallel inverters. This paper proposes an improved design of virtual output impedance loop for parallel three-phase voltage source inverters. In the approach, a virtual output impedance loop based on the decomposition of inverter output current is developed, where the positive- and negative-sequence virtual impedances are synthesized separately. Thus, the negative-sequence circulating current among the parallel inverters can be minimized by using a large negative-sequence virtual resistance even in the case of feeding a balanced three-phase load. Furthermore, to adapt to the variety of unbalanced loads, a dynamically-tuned negative-sequence resistance loop is designed, such that a good compromise between the quality of inverter output voltage and the performance of load sharing can be obtained. Finally, laboratory test results of two parallel three-phase voltage source inverters are shown to confirm the validity of the proposed method.
- ISBN:
- 9781467308021, 9781467308014
- Type:
- Conference paper
- Language:
- English
- Published in:
- Proceedings of the Ieee Energy Conversion Congress and Exposition 2012, 2012, p. 2466-2473
- Main Research Area:
- Science/technology
- Publication Status:
- Published
- Review type:
- Peer Review
- Conference:
- the Fourth IEEE Energy Conversion Congress and Exposition, ECCE 2012
- Publisher:
- IEEE Press
- Submission year:
- 2012
- Scientific Level:
- Scientific
- ID:
- 232636580