This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for systems on a chip or microcontrollers where processors run in parallel with embedded peripherals. We have developed a software tool, called CASTLE, to provide computer assistance in the design process of energy-aware embedded systems. The tool considers single processor and parallel architectures. An example shows an energy reduction of 23% when the tool allocates two microcontrollers for parallel execution.
Proc. of the Isca's 21st Lnternational Conference on Parallel and Distributed Computing and Communications Systems, 2008
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ISCA's 21st lnternational Conference on Parallel and Distributed Computing and Communications Systems (PDCCS-2008), 2008