1 Networks, Department of Photonics Engineering, Technical University of Denmark2 Department of Photonics Engineering, Technical University of Denmark3 Copenhagen Center for Health Technology, Center, Technical University of Denmark
This thesis focuses on network- andn ode architectuers for electrical and optical packet switched networks. Future packet switched networks could evolve towards many small, distributed units or towards fewer large, centralised switch units. This work assumes the latter evolution scenario and examines possible architectures for future high capacity networks with high capacity nodes. It is assumed that optics will play a key role in this scenario, and in this respect, the European IST research project DAVID aimed at proposing viable architectures for optical packet switching, exploiting the best from optics and electronics. An overview of the DAVID network architecture is given, focusing on the MAN and WAN architecture as well as the MPLS based network hierarchy. A statistical model of the optical slot generation process is presented and utilised to evaluate delay vs. efficiency. Furthermore, a benchmarking study has been carried out to compare power consumption of electrical and optical packet switches. The basic principles for Traffic Engineering and Quality of Service provisioning are discussed, and a simple scheme for Traffic Engineering in a best effort TCP/IP based nework is proposed. Also, Constraint Based Routing is examined, and the effect from taking the link load into account is evaluated. It is believed that electrical packet switching will satisfy demands in the coming years, and this work covers several aspects hereof. A new load balancing scheme for multipath packet switches is proposed where packets are collected and transmitted over identically parallel switch planes, eliminating the need for a packet re-ordering mechanism. An analytical result for the worst-case delay is derived, and the average performance is evaluated by a simulation study. Moreover, a new and more scalable architecture for a buffered crossbar switch is presented. The architecture uses two levels of backpressure (flow control) with different constraints on round trip time. No additional scheduling complexity is introduced, and for the actual example shown, a reduction in memory of 75% was obtained at the cost of an additional speedup of 10%. Lastly, the address lookup and classification problem is addressed, and an IP lookup algorithm with low memory requirement and fast updates is presented. The scheme uses a combination of trie and tree search, which is efficient in memory usage because the structure contains exactly one node for each prefix.